10 Way Electronic Switch

Description

This is a 10 way electronic latching switch using just two push-to-make switches. Each output can be latched on and off independently. 

Notes

The schematic is shown above, and two switches S1 and S2 are used to control the outputs. The main work is done by U2 a CMOS4017 decade counter divider IC. At switch on, C1 is quickly charged by R4 and a brief reset pulse is applied to to the reset pins of both U1 and U2. This results in U1, a 7 segment display display driver and decade counter showing "zero" on the 7 segment display and pin 3 (which is the output zero) of the 4017 becoming high.

Each time S1 is pressed the clock input of U2 is incremented, by one count and the display and 4017 will cycle through all 10 outputs. A separate reset switch is not provided as the display reads the currently selected output. Each output can be toggled (set or reset) independently by the use of a JK flip flop, a CMOS4027.

When the 4017 is on a particular output, for example zero, then the controlled circuit can be turned on or off using switch S2. To latch the output a type JK flip-flop is used at each of the ten outputs. The 4027 contains two JK flip flops, and only one flip flop is required per output. If you only required 5 outputs, then only three 4027 IC's are required. Three 4027 would give you six JK flip flops, the unused flip flop should have all unused inputs tied to ground.

The circuit works as follows. When the 4017 is at output zero, pin 3 will be high. This enables both JK inputs of the flip flop (U4A at output zero) and the circuit can then be toggled via pulses applied from switch S2. The 'Q' output of each flip-flop drives and NPN transistor and then a small relay. The NPN transistors can be any general purpose type, e.g. 2N2222, BC108, BC548 etc. The relay allows external loads of different voltage and current to this circuit to be controlled.

Pinouts

The pin numbers of the CMOS 4026 are shown on the diagram. The CMOS 4017 and CMOS 4027 are shown below:

Please note that VDD and VSS represent the drain and source power connections. The CMOS 4027 contains two JK Flip Flops, the pins S1, R1, J1, K1, CP1 represent the set, reset, J and K inputs and clock pulse inputs for one half of the 4027. The other flip flop is represented as S2, R2, etc. In the diagram U3A represents one JK flip flop or half of a 4027, and U4A and U4B use both JK flip flops or one complete 4027.

For clarity, the schematic is drawn with outputs, zero, six and nine shown only. The pinouts for the CMOS IC's 4017 and 4026 can be also be found in the practical section.

If required, the external circuits power supply can be used to power the driver transistor and relay. This is shown on output 6, the dotted lines representing the power coming from an external battery. The only other requirement here is that the external circuits common negative terminal is tied to this circuits common chassis (negative) terminal.